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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 0.3 / sep. 2004 1 hy57v643220d(l/ s)t(p) series 4banks x 512k x 32bits synchronous dram document title 4bank x 512k x 32bits synchronous dram revision history revision no. history draft date remark 0.1 initial draft may. 2004 preliminary 0.2 removed preliminary july 2004 0.3 1. updated output load capacitance for access time measurement cl = 30pf in ac operating test condition 2. updated the tolerance zone of the leads and the description of the package type in package dimension sep. 2004
this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 0.3 / sep. 2004 2 hy57v643220d(l/ s)t(p) series 4banks x 512k x 32bits synchronous dram description the hynix hy57v643220d(l/s)t(p) series is a 67,108,864bit cmos synchronous dram, ideally suited for the memory applications which require wide data i/o and high band width. hy57v643220d(l/s)t(p) is organized as 4banks of 524,228x32. hy57v643220d(l/s)t(p) is offering fully sy nchronous operation referenced to a positive edge of the clock. all inputs and outputs are synchronized with the rising edge of the clock input. the da ta paths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 1,2,4,8 or full page), an d the burst count sequence(se- quential or interleave). a burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or writ e command on any cycle. (this pipelined design is not re- stricted by a '2n' rule) features ordering information note 1. hy57v643220dt(p) series : normal power 2. hy57v643220dlt(p) series : low power 3. hy57v643220dst(p) series : super low power 4. hy57v643220d(l/s)t series : leaded 5. hy57v643220d(l/s)tp series : lead free part no. clock frequency organization interface package hy57v643220d(l/s)t(p)-45 222mhz 4banks x 512kbits x32 lvttl 86pin tsop-ii (lead free) hy57v643220d(l/s)t(p)-5 200mhz hy57v643220d(l/s)t(p)-55 183mhz hy57v643220d(l/s)t(p)-6 166mhz hy57v643220d(l/s)t(p)-7 143mhz ? voltage : vdd, vddq 3.3v supply voltage ? all device pins are compatible with lvttl interface ? jedec standard 400mil 86pin tsop-ii with 0.5mm of pin pitch ? all inputs and outputs refere nced to positive edge of system clock ? data mask function by dqm 0, 1, 2 and dqm 3 ? internal four banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ? burst read single write operation
rev. 0.3 / sep. 2004 3 hy57v643220d(l/s )t(p) series 4banks x 512k x 32bits synchronous dram 86pin tsop ii configuration 1 2 3 43 20 21 22 42 41 44 45 46 67 66 65 86 85 84 vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 vss nc dq31 vddq dq30 dq29 vssq dq28 dq27 vddq dq26 dq25 vssq dq24 vss vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vdd dqm0 /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 dqm2 vdd nc dq16 vssq dq17 dq18 vddq dq19 dq20 vssq dq21 dq22 vddq dq23 vdd 86pin tsop ii 400mil x 875mil 0.5mm pin pitch
rev. 0.3 / sep. 2004 4 hy57v643220d(l/s )t(p) series 4banks x 512k x 32bits synchronous dram pin function descriptions pin pin name description clk clock the system clock input. all other inputs are registered to the sdram on the rising edge of clk. cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables all inputs except clk, cke and dqm ba0, ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a10 address row address : ra0 ~ ra10, column address : ca0 ~ ca7 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation refer function truth table for details dqm0~3 data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq31 data input/output multip lexed data input / output pin vdd/vss power supply/ground power supply fo r internal circuits and input buffers vddq/vssq data output power/ ground power supply for output buffers nc no connection no connection
rev. 0.3 / sep. 2004 5 hy57v643220d(l/s )t(p) series 4banks x 512k x 32bits synchronous dram functional block diagram 512kbit x 4banks x 32 i/o low power synchronous dram internal row counter column pre decoder column add counter self refresh logic & timer sense amp & i/o gate i/o buffer & logic address register burst counter mode register state machine address buffers bank select column active row active cas latency clk cke cs ras cas we dqm0~3 a0 a1 ba1 ba0 a10 row pre decoder refresh dq0 dq31 x-decoder x-decoder x-decoder x-decoder y-decoder 512kx32 bank 0 512kx32 bank 1 512kx32 bank 2 512kx32 bank 3 memory cell array data out control pipe line control
rev. 0.3 / sep. 2004 6 hy57v643220d(l/s )t(p) series 4banks x 512k x 32bits synchronous dram basic functional description mode register ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000 op code 00 cas latency bt burst length op code a9 write mode 0burst read and burst write 1 burst read and single write burst type a3 burst type 0sequential 1interleave burst length a2 a1 a0 burst length a3 = 0 a3=1 00 0 1 1 00 1 2 2 01 0 4 4 01 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved cas latency a6 a5 a4 cas latency 0 0 0 r e s e r v e d 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 r e s e r v e d 1 1 0 r e s e r v e d 1 1 1 reserved
rev. 0.3 / sep. 2004 7 hy57v643220d(l/s )t(p) series 4banks x 512k x 32bits synchronous dram absolute maximum rating dc operating condition (t a = -40 to 85 o c ) note : 1. all voltages are referenced to v ss = 0v 2. v ih (max) is acceptable 5.6v ac puls e width with <=3ns of duration. 3. v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration ac operating test condition (t a = -40 to 85 o c , v dd =3.3 0.3v, v ss =0v) capacitance (t a = -40 to 85 o c , f=1mhz, v dd =3.3v) parameter symbol rating unit ambient temperature ta -40 ~ 85 o c storage temperature tstg -55 ~ 125 o c voltage on any pin relative to vss vin, vout -1.0 ~ 4.6 v voltage on vdd relative to vss vdd -1.0 ~ 4.6 v voltage on vddq relative to vss vddq -1.0 ~ 4.6 v short circuit output current ios 50 ma power dissipation pd 1 w soldering temperature . time tsolder 260 . 10 o c . sec parameter symbol min typ max unit note power supply voltage vdd, vddq 3.0 3.3 3.6 v 1 input high voltage vih 2.0 3.3 vddq+0.3 v 1, 2 input low voltage vil -0.3 - 0.8 v 1, 3 parameter symbol value unit note ac input high/low level voltage vih / vil 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise/fall time tr / tf 1 ns output timing measurement refe rence level voltage voutref 1.4 v output load capacitance for access time measurement cl 30 pf parameter pin symbol min max unit input capacitance clk ci1 2.5 3.5 pf a0 ~ a10, ba0, ba1, cke, cs , ras , cas , we , dqm 0~3 ci2 2.5 3.8 pf data input / output capacitance dq0 ~ dq31 ci/o 4 6.5 pf
rev. 0.3 / sep. 2004 8 hy57v643220d(l/s )t(p) series 4banks x 512k x 32bits synchronous dram note 1. dc characterristics i (t a = 0 to 70 o c ) note : 1. vin = 0 to 3.6v, all other balls are not tested under vin =0v 2. dout is disabled, vout=0 to 3.6 parameter symbol min max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -2ma output low voltage v ol -0.4v i ol = +2ma vtt=1.4v rt=500 ? 30pf output dc output load circuit ac output load circuit vtt=1.4v rt=50 ? 30pf output z0 = 50 ?
rev. 0.3 / sep. 2004 9 hy57v643220d(l/s )t(p) series 4banks x 512k x 32bits synchronous dram dc characteristics ii (t a = 0 to 70 o c ) note : 1. i dd1 and i dd4 depend on output loading and cycle rates. spec ified values are measured with the output open 2. min. of trc (refresh ras cycle time) is shown at ac characteristics ii 3. hy57v643220dt(p) series 4. hy57v643220dlt(p) series 5. hy57v643220dst(p) series parameter sym- bol test condition speed unit note 45 5 55 6 7 operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 220 200 190 180 170 ma 1 precharge standby cur- rent in power down mode i dd2p cke v il (max), t ck = 15ns 2 ma i dd2ps cke v il (max), t ck = 2ma precharge standby cur- rent in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 17 ma i dd2ns cke v ih (min), t ck = input signals are stable. 12 active standby current in power down mode i dd3p cke v il (max), t ck = 15ns 3 ma i dd3ps cke v il (max), t ck = 3 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 40 ma i dd3ns cke v ih (min), t ck = input signals are stable. 30 burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active cl=3 290 280 260 240 210 ma 1 auto refresh current i dd5 t rc t rc (min), all banks active 260 250 235 220 210 ma 2 self refresh current i dd6 cke 0.2v normal 2ma3 low power 0.8 ma 4 super low power 450 ua 5
rev. 0.3 / sep. 2004 10 hy57v643220d(l/s )t(p) series 4banks x 512k x 32bits synchronous dram ac characteristics i (ac operating conditions unless otherwise noted) note : 1. assume t r / t f (input rise and fall time) is 1ns. if t r & t f > 1ns, then [(t r +t f )/2-1]ns should be added to the parameter. 2. access time to be measured with input signal s of 1v/ns edge rate, from 0.8v to 2.0v. if t r > 1ns, then (t r /2-0.5)ns should be added to the parameter. parameter symbol 45 5 55 6 7 unit note min max min max min max min max min max system clock cycle time cas latency=3 t ck3 4.5 1000 5.0 1000 5.5 1000 6.0 1000 7.0 1000 ns cas latency=2 t ck2 10 10 10 10 10 ns clock high pulse width t chw 1.75 - 2.0 - 2.25 - 2.5 - 3.0 - ns 1 clock low pulse width t clw 1.75 - 2.0 - 2.25 - 2.5 - 3.0 - ns 1 access time from clock cas latency=3 t ac3 -4.5-4.5-5.0-5.5-5.5 ns 2 cas latency=2 t ac2 -6.0-6.0-6.0-6.0-6.0 ns data-out hold time t oh 1.5 - 1.5 - 2.0 - 2.0 - 2.0 - ns data-input setup time t ds 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - ns 1 data-input hold time t dh 0.8 - 1.0 - 1.0 - 1.0 - 1.0 - ns 1 address setup time t as 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - ns 1 address hold time t ah 0.8 - 1.0 - 1.0 - 1.0 - 1.0 - ns 1 cke setup time t cks 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - ns 1 cke hold time t ckh 0.8 - 1.0 - 1.0 - 1.0 - 1.0 - ns 1 command setup time t cs 1.3 - 1.5 - 1.5 - 1.5 - 1.75 - ns 1 command hold time t ch 0.8 - 1.0 - 1.0 - 1.0 - 1.0 - ns 1 clk to data output in low-z time t olz 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - ns clk to data output in high-z time cas latency=3 t ohz3 -4.0-4.5-5.0-5.5-5.5ns cas latency=2 t ohz2 -6.0-6.0-6.0-6.0-6.0ns
rev. 0.3 / sep. 2004 11 hy57v643220d(l/s )t(p) series 4banks x 512k x 32bits synchronous dram ac characteristics ii (ac operating conditions unless otherwise noted) note : 1. a new command can be given t rc after self refresh exit. parameter sym- bol 45 5 55 6 7 unit note min max min max min max min max min max ras cycle time operation t rc 58.5 - 55 - 55 - 60 - 63 - ns ras cycle time auto refresh t rrc 58.5 - 55 - 55 - 60 - 63 - ns ras to cas delay t rcd 18 - 15 - 16.5 - 18 - 20 - ns ras active time t ras 40.5 100k 38.7 100k 38.7 100k 42 100k 42 100k ns ras precharge time t rp 18 - 15 - 16.5 - 18 - 20 - ns ras to ras bank active delay t rrd 9 -10-11-12-14-ns cas to cas delay t ccd 1-1-1-1-1-clk write command to data-in delay t wtl 0 -0 -0 -0 -0 -clk data-in to precharge command t dpl tbd-tbd-tbd- 1 - 1 -clk data-in to active command t dal t dpl + t rp dqm to data-out hi-z t dqz 2-2-2-2-2-clk dqm to data-in mask t dqm 0-0-0-0-0-clk mrs to new command t mrd 2-2-2-2-2-clk precharge to data output high-z cas latency=3 t proz3 3-3-3-3-3-clk cas latency=2 t proz2 --2-2-2-2-clk power down exit time t dpe 1-1-1-1-1-clk self refresh exit time t sre 1-1-1-1-1-clk1 refresh time t ref -64-64-64-64-64ms
rev. 0.3 / sep. 2004 12 hy57v643220d(l/s )t(p) series 4banks x 512k x 32bits synchronous dram command truth table command cken-1 cken cs ras cas we dqm addr a10/ap ba note mode register set h x l l l l x op code no operation h x hx xx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single-write h x l l l l x a9 ball high (other balls op code) mrs mode self refresh 1 entry h l l l l h x x exit l h hx xx x lhhh precharge power down entry h l hx xx x x lhhh exit l h hx xx x lhhh clock suspend entry h l hx xx x x lvvv exit l h x x
rev. 0.3 / sep. 2004 13 hy57v643220d(l/s )t(p) series 4banks x 512k x 32bits synchronous dram package information jedec standard 400mil 86pin ts op-ii with 0.5mm pin pitch 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 22.327(0.8790) 22.149(0.8720) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 1.194(0.0470) 0.991(0.0390) unit : mm(inch) 0.150(0.0059) 0.050(0.0020) 0.50(0.0197) 0.21(0.008) 0.18(0.007) 0.05 0.05 m

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